This invention relates to a voltage selection circuit adapted to select different levels of voltages.
Recently, liquid display elements have been used in the multidigit display sections of, for example, a desk-top type electronic calculator, electronic timepiece etc. where numerals, marks etc. are displayed. Where a multi-digit liquid crystal display element is driven for display, an AC dynamic drive is adopted as a method for extending a service life of the liquid crystal. Since, for example, a one half or one third bias drive system is used as such, it is necessary to select a multi-level (for example, four-valued) voltage according to display data and supply it between two electrodes between which the liquid crystal element is interposed. Even in the electronic type printing device etc. of, for example, ink jet type printing devices etc., it is necessary to effect a D-A conversion of a character signal from a character signal generating circuit and sequentially provide a different voltage signal to a deflection electrode according to the character signal.
Such a conventional voltage selection circuit is constituted, for example, as shown in FIG. 1. FIG. 1 shows a circuit arrangement in which eight kinds of voltages V.sub.0 to V.sub.7 are selected. In the circuit arrangement shown in FIG. 1 a decoder 1 consists of, for example, inverters 2a to 2c and NAND circuits 3a to 3h. A code signal (A.sub.0, A.sub.1, A.sub.2) for voltage selection is applied to the input terminal of the decoder 1. The decoder 1 decodes the binary coded signal and generates an output signal which is applied to any one of the NAND circuits 3a to 3h. The outputs of the NAND circuits 3a to 3d are coupled directly to the P-channel MOS transistors 4a to 4d and the outputs of the NAND circuits 3e to 3h are coupled to the N-channel MOS transistors 4e to 4h through inverters 5a to 5d. Voltages V.sub.0 to V.sub.7 of different level are simultaneously supplied to the source electrodes of the transistors 4a to 4h and the drain electrodes of the transistors 4a to 4h are connected to an output terminal 6.
When in the circuit arrangement shown in FIG. 1 the code signal (A.sub.1, A.sub.2, A.sub.3) is applied, a signal is generated from one of the NAND circuits 3a to 3h in the decoder 1, causing a corresponding one of the MOS transistors 4a to 4h to be turned ON. By so doing a voltage being applied to the source electrode of its MOS transistor appears at the output terminal 6. In this way, a different level of voltages V.sub.0 to V.sub.7 is selected according to the code signal (A.sub.1, A.sub.2, A.sub.3) and a corresponding output emerges from the output terminal 6.
In such conventional voltage selection circuit it is necessary to provide a decoder and a gate circuit adapted to be operated by the decoder. Furthermore, a large number of circuit elements are involved, resulting in a complicated circuit arrangement. Since C-MOS transistors (complementary MOS transistors) are used for the gate circuits and C-MOS transistors are not used for the other circuits, a greater amount of electric power is involved.